1. Field of the Invention
The invention relates to a flash memory device and a programming method thereof. Particularly, the invention relates to a NAND flash memory device and a programming method thereof.
2. Description of Related Art
FIG. 1 is a block diagram of a typical NAND flash memory device. Referring to FIG. 1, the NAND flash memory device 100 includes a memory cell array 110, a row decoder 120 and page buffers 131-133. The memory cell array 110 includes a plurality of memory cell strings, and each of the memory cell strings includes a selection transistor, a plurality of memory cells and a ground transistor connected in series. For example, a memory cell string 140 includes a selection transistor SW11, a plurality of memory cells 151, 161-163 and a ground transistor SW12 connected in series.
Moreover, the row decoder 120 is electrically connected to the memory cell array 110 through a string selection line SSL1, word lines WL11-WL14, and a ground selection line GSL1. The page buffers 131-133 are electrically connected to the memory cell array 110 through bit lines BL11-BL16. During a programming process, the row decoder 120 selects one of the word lines according to address data. Moreover, each of the page buffers is electronically connected to two bit lines, and alternately provides a ground voltage Vs1 and a power voltage Vc1 to the two bit lines. Moreover, when the bit line WL12 is selected, the row decoder 120 provides a programming voltage Vp1 to the selected word line WL12, and provides a pass voltage Vt1 to the unselected word lines WL11 and WL13-WL14.
In this way, as shown in FIG. 1, during a front half period of the programming operation, the page buffers 131-133 provide the ground voltage Vs1 to the odd bit lines BL11, BL13 and BL15, and provide the power voltage Vc1 to the even bit lines BL12, BL14 and BL16. Then, the odd memory cells 151, 153 and 155 connected to the word line WL12 are programmed. In order to avoid influencing the memory cells 152, 154 and 156 located on the same word line WL12, a channel voltage of each of the memory cell strings can be boosted to avoid variations of threshold voltages of the memory cells 152, 154 and 156, which is the so-called program disturbance.
Generally, according to an existing memory operating method, the channel voltage of each of the memory cell strings is boosted by increasing the pass voltage Vt1 provided by the row decoder 120, so as to reduce the program disturbance. However, if the pass voltage Vt1 provided by the row decoder 120 is excessively high, the threshold voltages of the memory cells 161-163, 171-173 and 181-183 respectively located on the same bit line with the memory cells 151, 153 and 155 are influenced, which is the so-called pass disturbance. In other words, although the existing memory operating method resolves the problem of program disturbance by increasing the pass voltage, the pass disturbance is increased. Therefore, how to reduce the program disturbance in consideration of the pass disturbance is an important issue to be developed in memory operation.